library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;

entity mux50bit is
	port(a,b:	in std_logic_vector(0 to 49);
		s:	in std_logic;
		muxout:	out std_logic_vector(0 to 49));
end mux50bit;

architecture struct of mux50bit is
begin
muxarray:
	for i in 0 to 49 generate
		mux: muxout(i)<=(not s and a(i))or(s and b(i));
	end generate;
end struct;